The present invention relates to solid-state imaging apparatus, and more particularly relates to solid-state imaging apparatus using amplified MOS sensor.
Among the solid-state imaging apparatus in recent years, those solid-state imaging apparatus referred to as amplified MOS sensor are mounted on low power-consumption solid-state imaging apparatus to be used in mobile equipment or on high-resolution electronic still cameras. For existing solid-state imaging apparatus using amplified MOS sensor, methods of reading pixel area by the unit of row and effecting parallel processing with using column amplifiers that are provided for each column have been proposed to concurrently attain an increase in the number of pixels, higher frame rate, and lower noise. Systems capable of black level correction at column amplifier have also been proposed to further reduce noise.
In FIG. 1, solid-state imaging apparatus as disclosed in Japanese Patent Application Laid-Open 2005-143078 is cited as an example of solid-state imaging apparatus having construction of the above described system where black level correction is possible at the column amplifier. Specifically, the solid-state imaging apparatus shown in FIG. 1 includes: a pixel section 2 where pixel cells 1 are two-dimensionally disposed in row direction and column direction; a vertical scanning section 3 for selecting row to be read out of the pixel section 2; a vertical signal line 8 for outputting pixel signal by the unit of row from the pixel section 2; a column amplifier section 5 connected to the vertical signal line 8 to amplify pixel signal; a column amplifier drive section 4 for controlling operation of the column amplifier section 5; a horizontal select section 6 for outputting signal amplified at the column amplifier section 5; a horizontal scanning section 7 for selecting column to be read out of the horizontal select section 6; horizontal signal lines 9-1 to 9-n; a multiplexer 11 for selecting one of the horizontal signal lines 9-1 to 9-n; a multiplexer output terminal 12 for outputting signal selected at the multiplexer 11; and a black level control section 10 for controlling voltage to be applied on the column amplifier section 5 based on black level signal of the multiplexer output terminal 12. It should be noted that what is denoted by 8a in FIG. 1 is a bias current supply connected to the vertical signal line 8.
The pixel cell 1 includes: a photodiode PD serving as photoelectric conversion section; a transfer transistor M1 for transferring electric charge generated at photodiode PD to a accumulation section FD; a reset transistor M2 for resetting electric charge signal accumulated at the accumulation section FD; an amplification transistor M3 for amplifying the read out electric charge signal; and a row select transistor M4 for selecting each row.
The vertical scanning section 3 is to output: transfer control signal φ TX1, φ TX2 for controlling operation of the transfer transistor M1; reset control signal φ RS1, φ RS2 for controlling operation of the reset transistor M2; and row select control signal φ SEL1, φ SEL2 for controlling operation of the row select transistor M4. It should be noted that the pixel section 2 in this case is constructed by two pixel rows.
The column amplifier section 9 for each unit column includes: an inverting amplifier A11; a clamp capacitor C11 for retaining reset component of pixel signal; a feedback capacitor C12 for amplifying pixel signal; a sample-and-hold switch SW10 for connecting between the clamp capacitor C11 and an input terminal of the inverting amplifier A11; a switch for precharge SW12 for applying on the feedback capacitor C12 a clamp voltage Vcp which is an output voltage of the black level control section 10; a reset switch SW11 for resetting the clamp capacitor C11; a feedback capacitor connecting switch SW13 for connecting between the feedback capacitor C12 and an output terminal of the inverting amplifier A11; and a switch for hold SW14 for connecting output potential of the inverting amplifier A11 to a hold voltage supply Vhd which has a constant value.
The column amplifier drive section 4 outputs: a sample-and-hold control signal φ SH10 for controlling operation of the sample-and-hold switch SW10; an inverting amplifier reset control signal φ CL11 for controlling operation of the reset switch for inverting amplifier SW11; precharge control signal φ CL12 for controlling operation of the precharge switch SW12; and a feedback capacitor connection control signal φ SH11 for controlling operation of the feedback capacitor connection switch SW13.
FIG. 2 schematically shows drive timing. Shown here is case where a first row from the upper side of the pixel section 2 is selected by the vertical scanning section 3. At first, a reset level is outputted from the pixel cell 1. In particular, the row select transistor M4 is first turned ON by driving the row select control signal φ SEL1 to H level to connect the first pixel row to the vertical signal line 8. At the same time, after once turning ON the reset transistor M2 by driving the reset control signal φ RS1 to H level, the reset control signal φ RS1 is brought to L level to turn OFF the reset transistor M2. A reset level of pixel is thereby outputted onto the vertical signal line 8. The output voltage on vertical signal line 8 (V8) when pixel is in reset condition is referred to as Voff.
The operation of the column amplifier section 5 at this time will now be described by way of an example of the column amplifier on the left end. At first, inverting amplifier bias control signal φ P1 outputted from the horizontal scanning section 7 is driven to H level to bring the inverting amplifier A11 into its operating condition, and at the same time the hold switch SW14 is tuned OFF to disconnect an output terminal VA11 of the inverting amplifier A11 from the hold power supply Vhd. At the same time, the sample-and-hold switch SW10 is turned ON by driving the sample-and-hold control signal φ SH10 to H level to connect between the clamp capacitor C11 and the input terminal of the inverting amplifier A11. In addition, the reset switch SW11 is turned ON by driving the inverting amplifier reset control signal φ CL11 to H level to connect between the input terminal and the output terminal of the inverting amplifier A11. Further, the precharge control signal φ CL12 is driven to H level and the feedback capacitor connection control signal φ SH11 is brought to L level to turn ON the precharge switch SW12 so as to connect the feedback capacitor C12 to the clamp voltage Vcp. At the time of precharge, the output side voltage Vc12(pc) of the feedback capacitor C12 and output voltage VA11(pc) of the inverting amplifier A11 are represented by the following equations (1), (2).Vc12(pc)=Vcp  (1)VA11(pc)=Vat  (2)where Vat is reset voltage when the input terminal and the output terminal of the inverting amplifier A11 are connected to each other.
At this time, the clamp capacitor C11 retains output voltage Voff of the vertical signal line 8 in reset condition on the basis of reset voltage Vat of the inverting amplifier A11. Further, feedback capacitor C12 retains clamp voltage Vcp on the basis of reset voltage Vat of the inverting amplifier A11. Subsequently, the reset switch SW11 is turned OFF by bringing the inverting amplifier reset control signal φ CL11 to L level to disconnect between the input terminal and the output terminal of the inverting amplifier A11. At the same time, the precharge switch SW12 is turned OFF by bringing the precharge control signal φ CL12 to L level to disconnect the feedback capacitor C12 from the clamp voltage Vcp.
Subsequent to this, the feedback capacitor connection switch SW13 is turned ON by driving the feedback capacitor connection control signal φ SH11 to H level to connect between the feedback capacitor C12 and the output terminal of the inverting amplifier A11. At this time, a feedback loop is formed of the inverting amplifier A11 through the feedback capacitor C12, whereby the input terminal of the inverting amplifier A11 remains at Vat, and the output voltage VA11 of the inverting amplifier A11 attains the voltage accumulated at the feedback capacitor C12. Supposing this condition as reset condition, output voltage VA11(rst) of the inverting amplifier A11 in reset condition is obtained by the following equation (3).VA11(rst)=Vat+(Vcp−Vat)=Vcp  (3)
Next, signal level is outputted from the pixel cell 1. At first, in the condition where connection between the first pixel row and the vertical signal line 8 is kept by continuing H level of row select control signal φ SEL1, after turning ON the transfer transistor M1 by driving transfer control signal φ TX1 to H level to read signal electric charge accumulated at photodiode PD, the transfer control signal φ TX1 is brought to L level to turn OFF the transfer transistor M1. The signal level of pixel is thereby outputted onto the vertical signal line 8 through the amplification transistor M3 and the row select transistor M4. Supposing (−Vsig) as change in output voltage of the vertical signal line 8 from its reset condition to signal level condition, the output voltage of the vertical signal line 8 in its signal level condition is (Voff−Vsig).
The operation of the column amplifier section 5 at this time will now be described by way of an example of the column amplifier on the left end. When the vertical signal line 8 is changed corresponding to (−Vsig), since the inverting amplifier A11, clamp capacitor C11, and feedback capacitor C12 act as amplifier having an amplification factor (−C11/C12), the output voltage VA11(sig) of the inverting amplifier in its signal level condition is obtained by the following equation (4).
                                                                        VA                ⁢                                                                  ⁢                1                ⁢                                                                  ⁢                1                ⁢                                  (                  sig                  )                                            =                            ⁢                              Vcp                +                                                      (                                                                  -                        C                                            ⁢                                                                                          ⁢                                              11                        /                        C                                            ⁢                                                                                          ⁢                      12                                        )                                    ×                                      (                                          -                      Vsig                                        )                                                                                                                          =                            ⁢                              Vcp                +                                                      (                                          C                      ⁢                                                                                          ⁢                                              11                        /                        C                                            ⁢                                                                                          ⁢                      12                                        )                                    ×                                      (                    Vsig                    )                                                                                                          (        4        )            
Subsequently, the sample-and-hold control signal φ SH10 is brought to L level to turn OFF the sample-and-hold switch SW10 so that signal read period from pixel is ended by disconnecting between the clamp capacitor C11 and the input terminal of the inverting amplifier A11. Here, setting to an optimum black level is possible by adjusting the clamp voltage Vcp which is the output voltage of the black level control section 10. Further, by using variable capacitance device as the feedback capacitor C12 to make amplification factor variable, sufficient signal amplitude is obtained and favorable SN can be secured even when pixel signal level is small.
Next in reading signal from the column amplifier section 5 out to the horizontal signal line 9-1 to 9-n, read is effected sequentially from each column through the horizontal select switch SW21 selected by horizontal select signals φ H1, φ H2, . . . from the horizontal scanning section 7. At this time, inverting amplifier bias control signals φ P1 to φ Pn are sequentially driven to H-level condition to sequentially turn ON the inverting amplifier A11 of each column so that the horizontal signal lines 9-1 to 9-n are driven by the output of the inverting amplifier A11 itself.